FLOORPLAN

Introduction of Floorplan : 

• The process of determining which structures should be positioned closely together and allocating space so that they can perform as needed is known as floorplanning.

•  A suitable floorplan is chosen based on the hierarchy and the design area.     ( or )

• Floor planning is the process of creating an area for macros and standard cells to be placed

Inputs for floorplan:

1. Netlist (.v)

2. The techlef, or technology file

3. Timing Library files (.lib)

4. Physical library (.lef)

5. Synopsys design constraints (.sdc)

6. Tlu+

Steps in Floor Planning: 

1. Determine core height and breadth to estimate die size.

2. IO pad and port placement.

3. Creating a voltage area.

4. Macro placement.

5. Adding physical only cells

6. Pre-routing - power planning

Floorplan Control parameter :-

The core area is dependent on:

1. Aspect ratio : This determines the chip's size and shape. It's a ratio between vertical and horizontal route resources, or the proportion of height to width.

 
                                                                            Aspect ratio = width/height

2. Core usage : Utilization will specify the space taken up by the standard cells, macros, and other cells to the total area.

Eg : 

        80% of the core area is utilized if the core utilization is 0.8 in design by  arranging the macros, additional cells, and ordinary cells.

        The remaining 20% is utilized for Routing objectives.

                                                     core utilization = (macros area + std cell area +pads area)/ total core area

Types of macros :- 

Hard macros : Hard macros are those in which the circuit is fixed. We are unable to view the macro functionality details. we know the timing information.

Soft macros  :  We are able to observe the circuit's functionality and the kind of gates used inside it. We are also aware of the timing details.

NOTE :

A poor floor plan will result in Routing congestion and Die area waste.